AMD

AMD is the high performance and adaptive computing leader, powering the products and services that help solve the world’s most important challenges. Our technologies advance the future of the data center, embedded, gaming and PC markets.

Founded in 1969 as a Silicon Valley start-up, the AMD journey began with dozens of employees who were passionate about creating leading-edge semiconductor products. AMD has grown into a global company setting the standard for modern computing, with many important industry firsts and major technological achievements along the way.

Job Title:

SMTS- IP Verification Engineer

Last Date To Apply:

Not Specified

(Apply Link at the end)

ASAP, will end as soon as a certain number is reached

Experience Level:

Not Specified

Job Location:

Bangalore, India

Salary:

Not Specified

Eligible Batches:

Not Specified

Requirements:

PREFERRED EXPERIENCE:

• Proven experience designing logic blocks in CPU, GPU, NOC, or cache designs.
• Strong understanding of digital electronics and high-speed designs(>1GHz)
• Strong understanding of multi-processor coherency, memory ordering, i/o ordering, interrupts, MMU and caches
• Excellent knowledge of Verilog and System Verilog
• Good debugging and analytical skills
• Exposure to Design for Test, understanding of scan concepts and writing DFT friendly RTL
• Working knowledge of C, C++ and a scripting language like Perl or Python
• Working knowledge of x86 or ARM ISA is a plus

ACADEMIC CREDENTIALS:

• BS, MS, or PhD degree in Electrical or Computer engineering. Advance degree preferred.

Job Description:

• Early architectural/performance exploration through micro-architectural definition and design
• Optimize the design to meet power, performance, area, and timing requirements.
• Write easily readable and synthesizable Verilog RTL
• Run some unit level testing to deliver quality code to the Design Verification Team
• Create assertions to improve coverage and cover points to analyze coverage of the design.
• Create well written block level design documentation.
• Participate in post silicon functional and performance debug and tuning.
• Mentor junior engineers